The Verus Tool: A Quantitative Approach to the Formal Verification of Real-Time Systems1
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چکیده
The task of checking if a computer system satisfies its timing specifications is extremely important. These systems are often used in critical applications where failure to meet a deadline can have serious or even fatal consequences. This work describes Verus, an efficient tool for performing this verification task. Using our tool, the system being verified is specified in the Verus language and then compiled into a state-transition graph. A symbolic model checker allows the verification of untimed properties expressed in CTL [8]. Time bounded properties can be verified using RTCTL model checking [7]. Moreover, algorithms derived from symbolic model checking are used to compute quantitative information about the model [1]. The information produced allows the user to check the temporal correctness of the model: schedulability of the tasks of the system can be determined by computing their response time; reaction times to events and several other parameters of the system can also be analyzed by this method. This information provides insight into the behavior of the system and in many cases it can help identify inefficiencies and suggest optimizations to the design. The same algorithms can then be used to analyze the performance of the modified design. The evaluation of how the optimizations affect the design can be done before the actual implementation, significantly reducing development costs. Another advantage of our approach is that the Verus language has been especially designed to allow a straightforward description of the temporal characteristics of programs. This makes modeling real-time systems in Verus a simpler task.
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تاریخ انتشار 1997